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| HS-65647RH August 1995 Radiation Hardened 8K x 8 SOS CMOS Static RAM Functional Diagram AI ROW ROW DECODER 128 X 512 MEMORY ARRAY Features * 1.2 Micron Radiation Hardened SOS CMOS - Total Dose 3 x 105 RAD (Si) - Transient Upset >1 x 1011 RAD (Si)/s - Single Event Upset < 1 x 10-12 Errors/Bit-Day * Latch-up Free * LET Threshold >250 MEV/mg/cm2 * Low Standby Supply Current 10mA (Max) * Low Operating Supply Current 100mA (2MHz) * Fast Access Time 50ns (Max), 35ns (Typ) * High Output Drive Capability * Gated Input Buffers (Gated by E2) * Six Transistor Memory Cell * Fully Static Design * Asynchronous Operation * CMOS Inputs * 5V Single Power Supply * Military Temperature Range -55oC to +125oC * Industry Standard JEDEC Pinout I/O0 INPUT DATA CIRCUIT I/O7 E2 AI COL COLUMN I/O COLUMN DECODER E1 G W CONTROL CIRCUIT TRUTH TABLE E1 X 1 0 0 0 E2 0 1 1 1 1 G X X 1 0 X W X X 1 1 0 MODE Low Power Standby Disabled Enabled Read Write Description The Intersil HS-65647RH is a fully asynchronous 8K x 8 radiation hardened static RAM. This RAM is fabricated using the Intersil 1.2 micron silicon-on-sapphire CMOS technology. This technology gives exceptional hardness to all types of radiation, including neutron fluence, total ionizing dose, high intensity ionizing dose rates, and cosmic rays. Low power operation is provided by a fully static design. Low standby power can be achieved without pull-up resistors, due to the gated input buffer design. Ordering Information PART NUMBER HS1-65647RH-Q HS1-65647RH-8 HS1-65647RH/Proto HS1-65647RH/Sample HS9-65647RH-Q HS9-65647RH-8 HS9-65647RH/Proto HS9-65647RH/Sample HS9A-65647RH-Q TEMPERATURE RANGE -55oC -55oC to to +125oC +125oC 28 Lead SBDIP 28 Lead SBDIP 28 Lead SBDIP 28 Lead SBDIP 28 Lead Ceramic Flatpack 28 Lead Ceramic Flatpack 28 Lead Ceramic Flatpack 28 Lead Ceramic Flatpack 36 Lead Ceramic Flatpack DB NA PACKAGE -55oC to +125oC +25oC -55oC -55oC to to +125oC +125oC -55oC to +125oC +25oC -55oC to +125oC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Spec Number File Number 824 518729 2928.2 HS-65647RH Pinouts HS1-65647RH 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T28 TOP VIEW NC A12 A7 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 7 8 9 26 E2 25 A8 24 A9 23 A11 22 G 21 A10 20 E1 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 2 3 4 5 6 7 8 9 10 11 12 13 14 HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F28 TOP VIEW 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 NC A12 1 2 28 VDD 27 W A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 HS9A-65647RH 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K36.A TOP VIEW NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ0 DQ1 DQ2 GND 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ0 DQ1 DQ2 GND Spec Number 825 518729 Specifications HS-65647RH Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor. . . . . . . . . . . . 3mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Reliability Information Thermal Resistance JA JC 28 Lead SBDIP Package. . . . . . . . . . . . . 45oC/W 8.0oC/W 28/36 Lead Ceramic Flatpack Package. . 53.4oC/W 7.4oC/W Maximum Package Power Dissipation at +125oC Ambient 28 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W 28/36 Lead Ceramic Flatpack Package. . . . . . . . . . . . . . . . 0.94W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: 28 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . .22.2mW/C 28/36 Lead Ceramic Flatpack Package. . . . . . . . . . . . .18.7mW/C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range (VDD) . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . 0V to +0.2VDD Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . .0.8VDD to VDD Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VDD = 4.5V, IO = -5mA VI = VDD or GND VDD = 4.5V, IO = 8.0mA VI = VDD or GND VDD = 5.5V, VO = GND or VDD, VI = VDD or GND E1 = VDD, E2 = 0V GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 3 2 2 Input Leakage Current Standby Supply Current IIH or IIL IDDSB (Note 3) VDD = 5.5V, VI = VDD or GND VDD = 5.5V, IO = 0mA, VI = VDD or GND E1 = VDD, E2 = 0V 1, 2, 3 1, 3 2 2 Enable Supply Current IDDEN VDD = 5.5V, IO = 0mA, VI = VDD or GND E1 = 0.0V, E2 = VDD 3 1 2 Operating Supply Current (Note 2) IDDOP VDD = 5.5V, IO = 0mA, VI = VDD or GND, E2 = VDD, E1 = 0V, f = 2MHz VDD = 2.0V, IO = 0mA, VI = VDD or GND E1 = VDD, E2 = 0V 3 1 2 1, 3 2 2 Functional Tests Noise Immunity Functional Test NOTES: 1. All voltages referenced to device GND. 2. Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.) 3. In order for this device to be in low power standby mode. E2 must be disabled (low). FT FN VDD = 4.5V and 5.5V VI = VDD or GND, f = 1MHz VDD = 4.5, VIL = 0.2 VDD VIH = 0.8 VDD, f = 1MHz 7, 8A, 8B 7, 8A, 8B LIMITS TEMPERATURE C, +25 C, +85oC, +125oC -55oC, +25oC, +85oC, +125oC -55oC, +25oC +85 C +125 C -55 C, +25 C, +85oC, +125oC -55oC, +25oC +85 C +125 C -55 C +25 C +85oC, +125oC o o o o o o o o PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current SYMBOL VOH VOL IOZL or IOZH MIN VDD0.4 -10 -30 -60 -1.0 - MAX 0.4 10 30 60 1.0 500 4 10 77 73 64 100 86 75 50 1 4 - UNITS V V A A A A A mA mA mA mA mA mA mA mA A mA mA - -55o o -55oC +25oC +85oC, -55oC, +125oC +25oC Data Retention Supply Current IDDDR +85oC +125oC -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC Spec Number 826 518729 Specifications HS-65647RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Address Access Time Output Enable Access Time Chip Enable Access Time SYMBOL TAVQV TGLQV TE1LQV TE2HQV TWHAX TE1HAX TE2LAX TE1LE1H TE2HE2L TAVWL TAVE1L TAVE2H TWLWH TDVWH TDVE1H TDVE2L Data Hold Time Address Hold Time TWHDX TAVE1H TAVE2L TE2LDX TE1HDX NOTES: 1. AC measurements tested at worst case VDD. Guaranteed over full operating range. 2. AC measurements assume transition time 5ns; input levels = 0.0V to VDD; timing reference levels = 2.0V; output load = 1 TTL equivalent load and CL 50pF, for CL > 50pF, access times are derated 0.15ns/pF. 3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles. (NOTES 1, 2, 3) CONDITIONS VDD = 4.5V VDD = 4.5V VDD = 4.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC MIN MAX 50 15 50 UNITS ns ns ns Write Recovery Time VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 0 - ns Chip Enable to End-of-Write VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 35 - ns Address Setup Time VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 5 - ns Write Enable Pulse Width Data Setup Time VDD = 4.5V VDD = 4.5V VDD = 4.5V 9, 10, 11 9, 10, 11 9, 10, 11 -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC 25 30 30 - ns ns ns VDD = 4.5V VDD = 4.5V 9, 10, 11 9, 10, 11 -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC 0 40 - ns ns VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 0 - ns TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz I/O Capacitance CI/O VDD = Open, f = 1MHz VDD = Open, f = 1MHz Write Enable to Output in High Z TWLQZ VDD = 4.5V and 5.5V NOTES 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1 TEMPERATURE TA = +25oC TA = +25oC TA = +25oC TA = +25oC -55oC TA +125oC MIN MAX 12 12 12 12 10 UNITS pF pF pF pF ns Spec Number 827 518729 Specifications HS-65647RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Write Enable High to Output ON Chip Enable to Output ON SYMBOL TWHQX CONDITIONS VDD = 4.5V and 5.5V NOTES 1 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 0 MAX UNITS ns TE1LQX TE2HQX TGLQX VDD = 4.5V and 5.5V 1 0 - ns Output Enable to Output ON Chip Enable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change NOTES: VDD = 4.5V and 5.5V 1 0 - ns TE1HQZ TE2LQZ TGHQZ VDD = 4.5V and 5.5V 1 - 15 ns VDD = 4.5V and 5.5V 1 - 15 ns TAXQX VDD = 4.5V and 5.5V 1 0 - ns 1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to Flatpack device types only. 4. All measurements referenced to device GND. TABLE 4. POST 300K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Standby Supply Current SYMBOL IDDSB CONDITIONS VDD = 5.5V, IO = 0mA, E1 = VDD, E2 = 0V, VI = VDD or GND VDD = 5.5V, IO = 0mA, E1 = 0.0V, E2 = VDD, VI = VDD or GND VDD = 5.5V, IO = 0mA, f = 2MHz, E = 0V,VI = VDD or GND VDD = 2.0V, IO = 0mA, E = VDD TEMPERATURE +25oC MIN MAX 10 UNITS mA Enabled Supply Current IDDEN +25oC - 82 mA Operating Supply Current (Note 2) Data Retention Supply Current NOTES: IDDOP +25oC - 100 mA IDDDR +25oC - 6 mA 1. DC parameters not listed in this table are tested at the +25oC pre-irradiation test limits. All AC parameters are tested at the +25oC preirradiation test limits. 2. Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.) Spec Number 828 518729 HS-65647RH TABLE 5. BURN-IN DELTA PARAMETERS (+25oC), GROUP B, SUBGROUP 5 PARAMETER Standby Supply Current High Impedance Output Leakage Current Input Leakage Current Low Level Output Voltage Output High Voltage SYMBOL IDDSB IOZH, IOZL IIH, IIL VOL VOH DELTA LIMITS 150A 2A 150nA 60mV 150mV TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A (Note 1) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 RECORDED FOR -Q 1 (Note 2) 1, (Note 2) RECORDED FOR -8 TESTED FOR -Q 1, 7, 9 1, 7, 9, 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 TESTED FOR -8 1, 7, 9 1, 7, 9 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 1, 7, 9 Subgroup B5 Subgroup B6 Group C Sample 5005 Sample 5005 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, 1, 7, 9 N/A 1, 2, 3, (Note 2) N/A Group D Group E, Subgroup 2 NOTES: Sample 5005 Sample 5005 1, 7, 9 1, 7, 9 - 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only Spec Number 829 518729 HS-65647RH Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125oC Min, Method 1015 NOTES: 1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group Samples, Group D Test and Group D Samples. 5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 6. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * Group B and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 1) 100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 2(T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 2) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 3) Sample - Group B, Method 5005 (Note 4) Sample - Group D, Method 5005 (Notes 4 and 5) 100% Data Package Generation (Note 6) Spec Number 830 518729 HS-65647RH Intersil Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% External Visual 100% Initial Electrical Test 100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 2) Sample - Group B, Method 5005 (Note 3) Sample - Group C, Method 5005 (Notes 3 and 4) Sample - Group D, Method 5005 (Notes 3 and 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Group B, C and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 831 518729 HS-65647RH Timing Waveforms TAVAX A ADDRESS 1 TAVQV ADDRESS 2 TAXQX DATA 1 DATA 2 Q FIGURE 1. READ CYCLE I: W, E2 HIGH; G, E1 LOW TAVAX A TAVQV E1 TE1LQV TE1LQX E2 TE2HQV TE2HQX G TGLQV TGLQX Q TGHQZ TE2LQZ TE1HQZ FIGURE 2. READ CYCLE II: W HIGH TAVAX A TAVWL W TWLWH TWHAX E1 E2 TWHQX TDVWH D TWLQZ Q TWHDX FIGURE 3. WRITE CYCLE I: LATE WRITE Spec Number 832 518729 HS-65647RH Timing Waveforms (Continued) TAVAX A TAVE1L W TE1LE1H TAVE2H TE1HAX E1 E2 TDVE1H TE1HDX D FIGURE 4. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1 TAVAX A TAVE2H W TE2HE2L TAVE2L TE2LAX E1 E2 TDVE2L D TE2LDX FIGURE 5. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 Spec Number 833 518729 HS-65647RH Performance Curves HS-65647RH TYPICAL PERFORMANCE CHARACTERISTICS TA = +25oC, Unless Otherwise Specified 13 12 11 10 9 IDDSB (mA) IDDSB (mA) 5 4 3 2 1 0 0 200 400 600 800 1000 TOTAL DOSE (KRAD) 1200 1400 0.1 0.1 10 ANNEAL TIME (HOURS) 100 6 7 8 7 6 5 4 3 2 1 0 FIGURE 6 10 9 8 7 IDDSB (mA) IDDEN (mA) 6 5 4 3 2 1 0 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 120 100 90 80 70 60 50 40 30 20 10 0 -60 -40 -20 0 FIGURE 7 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 8 120 106 110 100 90 IDDOP (mA) IDDOP (mA) 80 70 60 50 40 30 20 -60 -40 -20 0 20 40 60 80 100 120 102 98 94 90 86 82 78 74 70 66 62 58 0 1 2 3 FIGURE 9 4 5 6 7 8 9 10 TEMPERATURE (oC) FREQUENCY (MHz) FIGURE 10 FIGURE 11 Spec Number 834 518729 HS-65647RH Burn-In Circuits HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP VDD 1 1 NC F13 F8 F7 F6 F5 F4 F3 9 F2 F1 F14 F14 F14 R2 R2 R2 10 11 12 13 14 7 8 5 6 2 A12 3 A7 4 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 E2 W NC VDD 28 27 F0 26 25 F9 24 23 22 21 20 19 18 17 16 15 R2 R2 F14 R2 R2 R2 F14 F14 F14 NC 14 F0 F11 F14 NC 12 NC 13 F10 F12 NC 2 3 4 5 6 7 8 9 10 11 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP VDD DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10k 10%, except R2 = 47k 10% 3. VIH: VDD 0.5V, VIL: 0.4V 0.4V 4. F0 = 100kHz 10%, 50% Duty Cycle 5. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2 6. F0 = inverted F0 HS-65647RH 36 LEAD FLATPACK VDD 1 2 NC F13 F8 F7 F6 F5 F4 F3 F2 F1 F14 F14 F14 R2 R2 R2 NC 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS VSS VDD NC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS 36 35 34 33 F0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 R2 R2 R2 R2 R2 F14 F14 F14 F14 F14 F10 F12 F0 F11 F9 NC STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10k 10% HS-65647RH 36 LEAD FLATPACK VDD 1 2 NC 3 4 5 6 7 8 9 10 11 12 NC NC NC NC 16 17 18 13 14 15 VSS VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS VSS VDD NC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC NC NC NC NC NC DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10k 10%, except R2 = 4.7k 10% 3. VIH: VDD 0.5V, VIL: 0.4V 0.4V 4. F0 = 100kHz 10%, 50% Duty Cycle 5. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2 6. F0 = Inverted F0 STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10k 10% Spec Number 835 518729 HS-65647RH Irradiation Circuit HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP VDD NC 1 NC 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 DQ0 12 DQ1 13 DQ2 14 VSS VDD 28 W 27 E2 26 A8 25 A9 24 A11 23 G 22 A10 21 E1 20 DQ7 19 DQ6 18 DQ5 17 DQ4 16 DQ3 15 NOTES: 1. VDD = 5.5V 0.5V R = 10k 10% 2. Group E sample size is two die/wafer. Test Patterns MARCH (II)PATTERN After a background of zeros is written, each cell (from beginning to end in sequence) is read, written to a one and reread. When the array is full of ones each cell (from the end to the beginning) is read, restored to a zero and reread. After this the pattern is repeated but with complemented data. MASEST PATTERN (Multiple Address Select Pattern) A checkerboard pattern is written into the memory. Then the first cell is read, then its binary address complement is read. The second cell is read and then its binary address complement is read. This pattern of incrementing the address and then reading its binary address complement is repeated until the entire memory is read. This is then repeated but using a checkerboard bar pattern. GALROW PATTERN (Row Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the row. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. GALCOL PATTERN (Column Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the column. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. CHECKERBOARD BAR PATTERN and CHECKERBOARD A checkerboard is written (101010) into the memory and then the pattern is read back. This is then repeated but using complemented data. Spec Number 836 518729 HS-65647RH Metallization Topology DIE DIMENSIONS: 313 x 291 x 21 1mils METALLIZATION: Type: Al/Si/Cu Metal 1 Thickness: 7500A 2kA Metal 2 Thickness: 10kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.5 x 105 Amps/cm2 Metallization Mask Layout HS-65647RH (28) VDD (23) A11 (25) A8 (24) A9 (2) A12 (26) E2 (27) W (22) G NC VSS VDD A10 (21) E (20) NC (7) A3 (6) A4 (5) A5 (4) A6 VSS VDD A0 (10) (3) A7 NC DQ1 (12) DQ2 (13) VSS (14) DQ3 (15) DQ4 (16) D15 (17) DQ6 (18) DQ7 (19) NC A2 (8) A1 (9) DQ0 (11) VDD Spec Number 837 518729 HS-65647RH Packaging A K36.A 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.006 0.006 0.004 0.004 0.620 0.620 0.470 0.030 0.025 BSC 0.240 0.026 36 0.280 0.045 0.0015 6.10 0.66 36 MAX 0.138 0.013 0.010 0.011 0.008 0.640 0.640 0.660 0.490 MILLIMETERS MIN 0.15 0.15 0.10 0.10 15.75 15.75 11.94 0.76 0.64 BSC 7.11 1.14 0.04 MAX 3.51 0.33 0.25 0.28 0.20 16.26 8.64 16.76 12.45 NOTES 3 3 7 8 Rev. 0 5/18/94 e PIN NO. 1 ID AREA A -A- -B- D A b b1 S1 c b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS c1 D E E1 E2 E3 e k L BASE METAL b1 M M (b) SECTION A-A (c) Q S1 M N NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Spec Number 838 518729 HS-65647RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 839 |
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